1. Technical Field
This disclosure relates generally to integrated circuit layout, and more particularly to data correcting a hierarchical integrated circuit layout with accommodation of a long range critical dimension (CD) variation of a process in manufacturing an integrated circuit based on the layout.
2. Background Art
Over the last 20-30 years, as integrated circuit features have been shrinking in size, the fundamental tools of lithography have not scaled at the same rate. For example, recent technology nodes have employed 248 nm and 193 nm wavelength light sources, forcing the need for optical imaging systems with higher numerical aperture (NA). As the resolution limits of these tools are approached, there has been an increasing discrepancy between a pattern drawn on a photo mask, and the resulting printed wafer image in resist. To address this problem, the semiconductor industry has turned to techniques for data corrections like optical proximity correction (OPC).
Modern models-based OPC includes two major components, a model and a correction algorithm. The model includes mathematical representations of the optical and resist patterning process—it can be built empirically, based on measurements of special calibration patterns printed on wafers, or based on physical principals of optics and resist chemistry. Many currently employed models involve some combination of these approaches to achieve a mathematical solution which can fairly accurately predict post-litho wafer images based on given mask shapes. The second part of OPC is the correction algorithm used to manipulate drawn circuit layouts to create a set of mask shapes. The typical inputs to this algorithm are a set of wafer target shapes (shapes representing the designer's intent on wafer, or some variation of this layout) and a model. An iterative process is employed, where shapes are manipulated through a set of edge fragment movements, and repeated use of the model to investigate how each iteration would show if printed on a wafer. The basic idea is to gradually move each fragment of the layout shape in the correct direction, so that after some finite number of iterations, the resulting mask shapes, when run through the OPC model, will result in the desired wafer image.
A common challenge faced by all of the correction techniques and algorithms is that they generally all require very large computational cost and time. The computational cost of processing data for a critical layer (like POLY) on a 32 nm processor design could easily run into tens of thousands of CPU hours. There is great interest in the industry in reducing the computational cost, and the resulting time spent in the manufacturing flow associated with mask layout data processing.
One problem with OPC processing that contributes to high computational cost is the fact that although integrated circuit (IC) layouts are designed with a significant amount of hierarchy, leaf cells are often placed in differing contexts which will behave differently when run through the OPC model. This drives the need to flatten hierarchy to some degree, in order to provide differentiated corrections to different parts of the layouts. The radius that a model “looks out” or uses for calculation of an image for a given shape is called the optical radius or Radius of Interaction (ROI). The larger the optical radius is in a model, the more adjacent shapes are taken into account in the OPC model calculations, and the greater the likelihood that two shapes at a low level in the hierarchy will need to be treated differently and pushed up (or flattened) in the OPC hierarchy. The disadvantages of “flat” OPC processing are significant, particularly when compared to efficient hierarchical processing techniques. Another disadvantage of flat processing is that the resulting mask layout design is very flat, and subsequent post OPC processing steps become very computationally expensive.
The relative success of OPC has resulted in investigation of other semiconductor manufacturing processes and their systematic sources of variation. For example, the etch process is similar to the litho process in that one can theoretically model the etch process, and correct for systematic sources of variation by manipulating layout data in a tape-out flow, so that the mask shapes generated by etch correction and OPC correction will print uniformly and very close to the intended wafer target dimensions. FIG. 1 shows an example of a tape-out flow, where fn(L) indicates a respective model function of a step operation on layout L resulted from the immediately previous step.
With respect to systematic process variations in the tape-out flow, the ideal order to perform the corrections is in the reverse order of the corresponding processing steps. This is because corrections can be treated as performing inverse operations in the data to the effect of the process itself. For this reason, the natural place to perform corrections for long range critical dimension variation(s) like etch variations, CMP related variation, and those caused by other post-litho processing steps is before OPC in the tape-out flow (FIG. 1).
Many of the long range critical dimension (CD) variations being discussed are often thought to be pattern density related effects. Existing approaches propose correction schemes based on pattern density maps and on models which use these maps as inputs. A potential algorithm based on the existing approaches will be challenged in an attempt to establish a tape out flow connection methodology. When corrections for long range CD variations, the natural method will lead to data hierarchy flattening. If this flattening occurs before OPC, then the advantages of hierarchical OPC engines will be lost.
The technology art has often cited this as a principal barrier to performing corrections of long range CD variations in a cost efficient manner, since the penalty of data hierarchy flattening could potentially make OPC computations grow by orders of magnitude.